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Sheet目录3872

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225

XMEGA A [MANUAL]

8077I–AVR–11/2012

20.

SPI – Serial Peripheral Interface

20.1

Features

Full-duplex, three-wire synchronous data transfer

Master or slave operation

Lsb first or msb first data transfer

Eight programmable bit rates

Interrupt flag at the end of transmission

Write collision flag to indicate data collision

Wake up from idle sleep mode

Double speed master mode

20.2

Overview

The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It

allows fast communication between an XMEGA device and peripheral devices or between several microcontrollers. The

SPI supports full-duplex communication.

A device connected to the bus must act as a master or slave.The master initiates and controls all data transactions. The

interconnection between master and slave devices with SPI is shown in Figure 20-1 on page 225. The system consists of

two shift registers and a master clock generator. The SPI master initiates the communication cycle by pulling the slave

select (SS) signal low for the desired slave. Master and slave prepare the data to be sent in their respective shift

registers, and the master generates the required clock pulses on the SCK line to interchange data. Data are always

shifted from master to slave on the master output, slave input (MOSI) line, and from slave to master on the master input,

slave output (MISO) line. After each data packet, the master can synchronize the slave by pulling the SS line high.

Figure 20-1. SPI master-slave interconnection.

The SPI module is unbuffered in the transmit direction and single buffered in the receive direction. This means that bytes

to be transmitted cannot be written to the SPI DATA register before the entire shift cycle is completed. When receiving

data, a received character must be read from the DATA register before the next character has been completely shifted in.

Otherwise, the first byte will be lost.

In SPI slave mode, the control logic will sample the incoming signal on the SCK pin. To ensure correct sampling of this

clock signal, the minimum low and high periods must each be longer than two CPU clock cycles.

When the SPI module is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to

Table 20-1 on page 226. The pins with user-defined direction must be configured from software to have the correct

direction according to the application.

SHIFT

ENABLE

msb

lsb

msb

lsb

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